In general, when manufacturing a desired semiconductor device, a semiconductor wafer is subjected to time after time various heat treatments such as a film forming process, a pattern etching process, an oxidation/diffusion process, a quality modification process, an annealing process and the like. Recently, along with a recent trend of a high density, a multilayered structure and a high integration of semiconductor devices, a strict heat treatment process has been in demand. In particular, an improvement of in-surface uniformity of a wafer and a film quality improvement are required when performing various heat treatments.
For example, when processing a channel layer of a transistor as a semiconductor device, it is typical to perform an annealing process after implanting ions of impurity atoms into the channel layer in order to stabilize the atomic structure.
In this case, if the annealing process is performed for a long period of time, the atomic structure becomes stable, but the impurity atoms are diffused into deep portions of a film thickness direction, causing a downward penetration. To this end, the annealing process needs to be performed for a shortest period of time possible. Specifically, in order to stabilize the atomic structure while preventing the impurity atoms from penetrating through the channel layer of a thin film thickness, it is necessary to rapidly increase a temperature of the semiconductor wafer to a high temperature and then rapidly decrease the temperature thereof to a low temperature at which the diffusion does not occur.
In order to achieve the aforementioned desirable annealing process, a conventional processing equipment is provided with a lamp house accommodating therein a heating lamp and a shutter mechanism for blocking radiant heat from the heating lamp. Further, such conventional processing equipment is configured to perform the annealing process at a high temperature and then rapidly decrease the temperature of the wafer by blocking the radiant heat from the heating lamp by means of an operation of the shutter mechanism.
In another conventional processing equipment disclosed in Japanese Patent Laid-open Application No. 2001-85408, peltier elements are provided on a wafer stage. The peltier elements are used for increasing and decreasing a temperature of the wafer such that an etching process can be performed on the wafer in a temperature range of about 100 to 250° C.
When the peltier elements are used for increasing and decreasing a temperature of the wafer, about a few tens of peltier elements, each being a few millimeters in length, height and width, are arranged planarly, thereby forming one element module. Such an element module is used as one unit module. Moreover, a plurality of element modules are planarly arranged corresponding to a wafer area and then fixed to a planar susceptor by screws, thereby forming a heating unit.
After the wafer is mounted on the susceptor, the wafer can be heated by applying power to the peltier elements. Further, the wafer can be cooled by applying power to the peltier elements in the opposite direction of that in the heating process.
In the prior art described above, the susceptor and the element modules are fixed to each other by being strongly pressure-contacted by means of screws in order to enhance efficiency of heat conduction by minimizing a contact thermal resistance between top surfaces of the element modules and the susceptor. Accordingly, the susceptor fixed by the screws is not allowed to be thermally expanded or contracted. As a result, a thermal expansion of the susceptor may deform the susceptor to bend or may cause a breakage of the susceptor or the peltier elements.
Moreover, in the aforementioned prior art, the susceptor is positioned on the element modules and, then, the wafer is mounted on the corresponding susceptor. In other words, a thin plate shaped member, i.e., the susceptor, is placed between the wafer and the peltier elements. The presence of the thin plate shaped member limits the enhancement and the improvement of the heat conduction efficiency.